Semiconductor Cleanroom Guide
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This part of our website aims to provide a guide to the issues associated with non-sterile cleanrooms used in high-tech manufacturing, particularly the semiconductor wafer fabrication operations and adjacent sectors. Each section provides an overview of the topic, as well as links to further information. It is aimed at people who are new to the semiconductor sector, or those who work in the sector in non-technical roles and want an overview of some key issues.
In section 5, the terminology is mainly related to silicon-chip based manufacturing, but the concepts also apply to any small feature technology involving photolithographic pattern generation. So, for example, it applies to wide range of semiconductor and optoelectronics manufacturing using substrates, such as: Si, GaN, GaAs, SiC, LiNbO3 etc., and some plastic electronic operations and MEMS. Terms that are commonly used in silicon microchip fabrication have been used in this guide with some explanations regarding semiconductor equipment and processes.
Content List
1. Cleanroom Standards
1.1 Cleanroom Classification Principles
Cleanrooms are classified by the cleanliness of the air within them. The classification is determined in terms of the number of particles of a particular size per volume of air. Many other aspects of these rooms may be carefully engineered and controlled, such as temperature and humidity, the electrostatic discharge characteristics of the flooring and work stations, the wavelength of the lighting in certain areas, the extraction requirements of certain equipment due to thermal loading or hazardous chemicals, but cleanroom classification is purely concerned with the cleanliness of the air in terms of particulates.
For more details, this link provides a good overview of cleanroom classifications
1.2 Evolution of Cleanroom Standards
The boom in semiconductor technology took place in Silicon Valley California in the late 1960’s and 70’s and one of the consequences of this was that a hybrid standards system emerged whereby airborne particle counts use a combination of feet per minute, particles per cubic foot and particle sizes specified in microns. So, a class 100 cleanroom was one in which air flowed out of a HEPA (High Efficiency Particle Air) filter at 90 feet per minute and that one cubic foot of that air contained less than 100 particles greater than 0.5 microns in diameter. The American standard FED STD 209E built on this concept. Over time, new approaches were adopted to specify the allowed distributions of particles, as well as making the standards relevant to manufacturing in pharmaceuticals, semiconductors and other high-tech sectors.
FED STD 209E was cancelled in 2001 and superseded by worldwide recognised ISO standards of ISO 14644-1 and ISO 14698. Section 1.2 shows how the two different standards (FED and ISO) are related.
1.3 ISO 14644 – Cleanrooms (Series)
ISO 14644 is a series of international standards relating to cleanrooms. It provides a common approach for defining, classifying, and managing clean environments based on measurable air cleanliness criteria.
The purpose of the standard is to provide a consistent and internationally recognised method of describing cleanroom performance. Before ISO 14644 was introduced, cleanroom requirements were often defined using regional or industry-specific standards, which made comparison between organisations and facilities difficult. ISO 14644 was developed to harmonise these approaches and allow cleanroom performance to be specified and assessed using a common methodology worldwide.
ISO 14644 is used across a range of industries, including semiconductor and microelectronics manufacturing. In this context, it provides a shared technical language for defining cleanroom performance and forms the basis on which cleanrooms are specified, tested, monitored, and referenced throughout their operational life.
1.4 ISO 14644-1 – Airborne Particle Classification
ISO 14644-1 defines the classification of cleanrooms based on the concentration of airborne particles. Classification is determined by measuring particle concentrations at specified particle sizes within a defined volume of air and comparing the results against the limits set out in the standard.
Air cleanliness is expressed using a series of ISO cleanroom classes, ranging from ISO Class 1, which represents the highest level of air cleanliness, through to ISO Class 9, which represents the least stringent classification. A lower ISO class number corresponds to a lower allowable concentration of airborne particles and therefore a cleaner environment.
Table 1 shows the maximum allowable airborne particle concentrations for ISO cleanroom classes as defined in ISO 14644-1.
The scope of ISO 14644-1 is limited specifically to airborne particulate contamination. It does not define requirements for other environmental conditions such as temperature or humidity, nor does it address process performance or product quality. The standard simply provides a consistent and measurable basis for defining and verifying air cleanliness.
For background on the historical development of cleanroom classification systems, and the transition from US Federal Standard 209E to ISO-based classification, refer to Section 1.2.
In semiconductor and microelectronics manufacturing, particle size and concentration are particularly critical because device feature sizes may be comparable to, or smaller than, many common airborne particles. As feature sizes continue to decrease, progressively smaller particles can become yield-limiting or reliability-limiting.
1.5 ISO 14644-2 – Monitoring and Compliance
ISO 14644-2 builds on the air cleanliness classification defined in ISO 14644-1 by addressing how cleanroom performance is monitored and how continued compliance with a specified ISO class is demonstrated over time. Initial classification confirms that a cleanroom meets its required air cleanliness level at a particular point in time. However, cleanroom conditions can change during operation, and ongoing monitoring is therefore required.
The standard provides principles for establishing a monitoring strategy appropriate to the cleanroom classification, its application, and the associated operational risk. This includes consideration of monitoring locations, monitoring frequency, and the conditions under which measurements should be taken in order to provide confidence that air cleanliness remains within specified limits.
ISO 14644-2 also defines circumstances in which reclassification may be required. Changes to processes, equipment, airflow patterns, or cleanroom usage can all influence airborne particle levels. The standard therefore provides a framework for determining when formal reassessment of cleanroom classification is necessary.
1.6 ISO 14644-3 – Test Methods
ISO 14644-3 defines the test methods used to evaluate cleanroom performance. These methods support both initial classification and ongoing assessment by providing standardised procedures for measuring airborne particle concentration and other parameters relevant to cleanroom qualification.
The use of defined test methods ensures that cleanroom performance can be assessed in a consistent and repeatable way, allowing results to be compared over time and between different facilities. This consistency is particularly important in semiconductor manufacturing, where small changes in environmental conditions can have a measurable impact on yield and device reliability.
By establishing recognised test approaches, ISO 14644-3 underpins the credibility of cleanroom classification and monitoring activities. It provides the technical basis for verification, audit, and periodic assessment, and supports confidence that cleanroom environments continue to perform as intended.
1.7 ISO 14644-4 – Cleanroom Design, Construction and Start-Up
ISO 14644-4 focuses on the design, construction, and initial start-up of cleanrooms, ensuring contamination control is built into a facility from the earliest stages of its lifecycle. It provides guidance on how cleanrooms may be planned and delivered to support achievement of their intended ISO classification once operational.
The standard covers key considerations such as cleanroom layout and zoning, airflow concepts, material selection, and construction detailing, all with the aim of minimising particle generation and preventing contamination ingress. It also addresses the integration of HVAC systems and building services, recognising their critical role in maintaining controlled conditions in semiconductor cleanrooms.
ISO 14644-4 also applies during the build and start-up phase, outlining clean construction practices and checks that should be completed before formal classification and performance testing take place. By following this guidance, cleanroom operators can reduce the risk of costly redesigns, delays, or failures during qualification.
1.8 ISO 14644-5 – Cleanroom Operations
ISO 14644-5 focuses on cleanroom operations and the practices required to maintain air cleanliness during routine use. While classification and monitoring define acceptable limits for airborne contamination, ISO 14644-5 addresses how day-to-day activities within the cleanroom influence contamination levels and overall performance.
The standard provides guidance on operational practices that support contamination control, including personnel behaviour, material flow, equipment usage, and housekeeping. These factors have a direct impact on airborne particle generation and distribution and often become the dominant source of contamination once a cleanroom is in operation, particularly in high-sensitivity environments.
By linking cleanroom design intent with real operational behaviour, ISO 14644-5 recognises that a cleanroom can meet its specified classification yet still fail to perform if operational discipline is not maintained. In semiconductor manufacturing, consistent adherence to defined operational practices supports stable cleanroom conditions, reduces process variation, and helps protect yield and long-term device reliability.
1.9 ISO 14644-6 – Terminology and Definitions
ISO 14644-6 provides standardised terminology, symbols, and definitions used throughout the ISO 14644 cleanroom standards series. Its purpose is to ensure that terms related to cleanroom classification, design, testing, and operation are interpreted consistently across different parts of the standard and by different stakeholders.
1.10 ISO 14644-7 – Separative Devices, SMIF and Mini-Environments
ISO 14644-7 addresses the use of separative devices to create localised clean environments within or outside a cleanroom. These devices include clean air hoods, isolators, glove boxes, and mini-environments designed to provide enhanced contamination control around specific processes or products.
In semiconductor and microelectronics manufacturing, separative devices are commonly used to achieve higher levels of cleanliness at key process steps without requiring the entire cleanroom to operate at the same ISO class. This approach allows airborne particle exposure to be reduced where it matters most, while balancing facility complexity, energy use, and operational cost.
A key application of separative devices in semiconductor manufacturing is the protection of wafers during transport and transfer between process tools. Sealed wafer handling systems reduce wafer exposure to the surrounding cleanroom environment and help limit contamination during handling and equipment interfaces.
ISO 14644-7 provides a framework for defining, classifying, and assessing these localised environments, supporting their integration into broader cleanroom contamination control strategies.
Further detail on the historical development, implementation, and impact of SMIF systems and mini-environments in semiconductor wafer fabrication is discussed in
Section 3.6
.
1.11 ISO 14644-8 – Airborne Molecular Contamination (AMC)
ISO 14644-8 extends cleanroom contamination control beyond particulate matter by addressing airborne molecular contamination. Molecular contaminants, such as acids, bases, and organic compounds, can interact with sensitive surfaces and materials even when particulate cleanliness requirements are fully met.
Unlike particulate contamination, airborne molecular contamination is not detected using standard particle counting methods. As a result, a cleanroom may comply with ISO 14644-1 airborne particle classification limits while still containing molecular contaminants capable of affecting processes or materials.
In semiconductor and microelectronics manufacturing, airborne molecular contamination can influence process chemistry, surface reactions, and long-term device reliability. Sources of AMC may include construction materials, process chemicals, outgassing from equipment, and human activity within the cleanroom. ISO 14644-8 provides a framework that allows these contaminants to be assessed, specified, and controlled in a consistent manner.
By recognising molecular contamination as a distinct category, the standard supports a more complete approach to cleanroom environmental control. This is particularly important in advanced semiconductor processes, where non-particulate contamination can be yield-limiting or reliability-limiting, even in environments that meet the most stringent particulate cleanliness classifications.
1.12 ISO 14644-9 – Surface Particle Cleanliness
ISO 14644-9 addresses the classification of surface particle cleanliness, recognising that contamination on surfaces can be just as significant as airborne contamination. Particles deposited on work surfaces, tools, or components may be transferred to products during handling or processing, even when airborne particle levels are well controlled.
Surface particles are particularly problematic because they can be re-entrained into the airflow or transferred directly to products through routine handling, cleaning activities, or interaction with equipment. As a result, surface contamination can become a source of secondary airborne contamination or direct product defects if it is not properly managed.
The standard provides a framework for assessing surface cleanliness based on particle size and concentration, supporting a consistent and measurable approach to surface contamination control. This complements airborne particle classification by addressing contamination risks that arise after particles have settled and are no longer captured by airborne monitoring.
In semiconductor manufacturing, surface particle cleanliness is closely linked to handling practices, equipment design, and cleaning procedures. ISO 14644-9 therefore supports a more complete contamination control strategy when used alongside airborne cleanliness standards, helping to reduce defect risk and support stable process performance.
2. PPE Aspects of Semiconductor Manufacturing
2.1 Potential hazards in Semiconductor Manufacturing
The potential hazards incurred during the manufacture of semiconductor products are wide range. They include extremely high voltages (e.g. 200,000 volts), poisonous and/or explosive gases, strong acids, highly oxidizing substances, high pressure systems and vacuum systems, volatile solvents, radiation such as: x rays, ultraviolet, RF, and microwaves etc…
Much of the semiconductor sector is now very mature and most safety issues are well addressed by equipment manufacturers, wafer fab designers/builders and by the training given to engineers, technicians and operators. However, new employees and trainees are in a higher risk category as they may try to address a problem without fully understanding the safety issues. For example someone discovering a spillage of a highly oxidizing liquid, such as the dopant source POCl3 might reach for a handful of cellulose based non-woven wipers to wipers to contain it without realizing that they are creating a potential fire hazard (see 11.1.6 https://pubchem.ncbi.nlm.nih.gov/compound/Phosphorus-oxychloride#section=Fire-Hazards). So, if you are new to this industry take great care in dealing with unexpected abnormal events and situations and always report issues to the Emergency Response Team and/or your safety manager rather than trying to tackle them yourself.
In addition, there are the more traditional issues found in any workplace such as trip/slip hazards etc. Wafer fabs also need high levels of temperature and humidity environmental control, as part of the photolithography process, and this requires cooling towers that need to be routinely treated to protect the workforce and any nearby public from legionella.
This link takes you to a comprehensive article regarding health hazards in the semiconductor industry ( https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4090871/ ) . The link provides information from the international Journal of Environmental Health 2014 Apr; 20(2):95-114
There are probably few if any firms that provide PPE covering all of the hazards mentioned above. However, Lynbond does address several of them, including protection against specific acids and solvents used in wafer fabs, as well as harmful dust inhalation. The products below have detailed specification sheets that allow appropriate choices to be made. And the Lynbond web site also allows you to search for products with specific EN numbers.
For acid aprons/coveralls click Disposable Clothing & Accessories
For a range of cleanroom chemical gloves click Chemical Protection Gloves
For eye protection click here
For PPE face masks click Facemasks
For a comprehensive table of PPE gloves covering acids and solvents click MAPA Gloves for the MAPPA range of products.
3. Overview of why cleanrooms are needed in order to make microchips and discrete electronic components
3.1 The need for cleanrooms in microchip manufacturing
A central element of microchip production is a printing process using a photographic technique called photolithography. Patterns are printed on to semiconducting substrates (such as silicon) many times during chip manufacture. These patterns cover the substrate in an array, looking rather like a sheet of postage stamps. Each pattern in the array has the potential to become a fully functioning microchip, but any flaw in the pattern may cause it to fail.
A silicon wafer covered in microchips
The first patterns to be printed on the substrate have features that are relatively large and each subsequent pattern has smaller and smaller features until the manufacturing stage reaches the point where tiny holes are created through which conducting layers join up the various parts of the electronic circuit. These holes are called contact holes and are typically the smallest feature on the chip. The image below shows metal tracks that join up individual parts of the electronic circuit. The small oblong features within the tracks are the contact holes. The holes are formed within insulating layers that allow the metal to make contact with the semiconductor below.
A small portion of a microchip showing the conducting metal tracks that join up components to create an integrated circuit (i.c)
The microchip is made up of layer upon layer of material, with each layer being patterned using a process called photoengraving that involves photographic and etching techniques. The details of how the layers are deposited and how they are etched is beyond the scope of this section. However, the printing process and various additional sophisticated processing allows patterns to be created in each of the deposited layers. The image below shows an idealised three-dimensional schematic of part of a microchip. It gives an idea of how patterned layers are built up to create a complex tangle of various materials that forms the electronic circuit.
A 3D schematic illustrating the complex layering of a microchip and an actual cross section
In many cases, the components within a microchip operate at low voltage and with tiny electrical currents. What this meant in the early days of the industry was that the patterns being printed were larger than they needed to be. As a result, there was a technological race to achieve improved printing capabilities. At the end of the 1970’s the smallest features (usually the contact holes and the metal tracks that joined them) were 5 microns wide. By 2020 features 500 times smaller were possible, with lines as narrow as 10 nm being printed in the leading-edge wafer fabs.
The graph shows the ability to create features of a particular size (the red shows the wavelength of light used in the processing)
Finally, we get to answer the question of why microchips are made in cleanrooms. The answer is that airborne particles landing on the substrates (e.g. silicon wafers) during microchip manufacturing caused defects in the printing process that meant that the microchips failed to operate properly. The ratio of the number of chips on a silicon wafer that work compared to the total number on the wafer is called the die yield. And sometimes, in the early days, the yield could be less than 10%. In other words, 90% of the chips on a completed silicon wafer could be scrap.
Every microchip on this wafer was tested against a specification, those with black dots on them failed and are scrap.
3.2 The sources of airborne particles that corrupt microchip functionality
The corruption of the printed patterns on a semiconductor wafer could be due to many causes. Some of the causes are due to process/equipment limitations that might produce a non-random scatter of defects. Other defects, such as airborne particles, are of a more random nature. Imagine a silicon wafer that has 1000 completed microchip patterns printed onto it and has accumulated 100 randomly positioned defects due to airborne particles. In this case at least 900 of the chips will not be affected by the 100 random defects, so the yield will be over 90%. Now consider the case where the microchips were much larger, for example if only 10 microchips were printed onto the silicon wafer, then 100 random defects would mean that probably all those chips would fail. The point is that airborne particles can have a dramatic impact on the levels of scrap produced during microchip manufacturing.
In fact, as chip sizes increase and the feature size on the chips decrease then scrap due to airborne particles rapidly increases. So, the aim of cleanrooms is to control airborne particles in order to reduce the levels of defects that cause microchips to fail. Note also that not all defects cause the chips to fail, those that do are called killer defects. Some defects do not immediately cause failure in the chip but might reduce its reliability. There are also some defects that are visually undesirable, but which are benign.
3.3 Yield, Defect Density and Killer Defects
Airborne particles landing on the semiconductor wafer might corrupt the chip pattern, or they might interfere with the deposited layer causing a void, or, as in the image below they might create a potential electrical short circuit between two conducting metal tracks etc...
The nature of the particles causing problems can be wide range and the image below shows the types of airborne particles that cleanrooms try to eliminate.
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